1. Field of the Invention
The present invention relates to passive integrated circuits comprising, at the surface of a substrate, a stack of alternated insulating and conductive layers forming passive components such as inductances, capacitors, and couplers.
2. Discussion of the Related Art
Chips or integrated devices assembling passive components are known, which are specifically adapted to performing filtering, coupling, transformation, etc. functions. Such devices comprise, at the surface of a substrate, for example, a glass or silicon substrate, a stack of alternated insulating and conductive layers. These layers are etched to form desired elementary passive components. The components are interconnected via conductive tracks and vias formed in the stack of conductive and insulating layers. Further, conductive contact pads are provided at the surface of the stack to provide connections to the outside of the chip.
FIG. 1 is an electric diagram of a very simple passive circuit. It is a bandpass filter LC circuit. An inductance 10 is connected between terminals 14 and 15, and two capacitors 12 and 13 in series are connected between terminals 14 and 15, parallel to inductance 10.
FIGS. 2A to 2D schematically show an integrated circuit chip 20 corresponding to an embodiment of the circuit of FIG. 1. FIG. 2A is a top view, and FIGS. 2B, 2C, and 2D respectively are cross-section views along planes B-B, C-C, and D-D of FIG. 2A. It should be noted that the top view and the cross-section views do not strictly correspond. In particular, in the top view, the contours of some regions have been expanded or contracted to more easily make out these regions from corresponding regions of other metallization levels.
As appears from the cross-section views (FIGS. 2B to 2D), chip 20 comprises, at the surface of a substrate 21, a stack 23 of conductive and insulating layers. Stack 23 comprises, at a first distance from the surface of substrate 21, conductive copper regions of a first metallization level M1, and above level M1, other conductive copper regions of a second metallization level M2, with an insulating layer separating level M2 from level M1.
Chip 20 comprises a conductive winding 10 formed of a copper track of level M1. Winding 10 corresponds to inductance 10 of the diagram of FIG. 1.
As illustrated in FIGS. 2A and 2D, each of capacitors 12 and 13 of the diagram of FIG. 1 is formed of the stack of a lower electrode 24, of a layer of a dielectric material (respectively 26 and 27), and of an upper electrode (respectively 28 and 29). Lower electrode 24 is common to capacitors 12 and 13, thus creating a series connection between capacitors 12 and 13. Lower electrode 24 is formed of a conductive region, for example, made of copper, of a level lower than level M1, and upper electrodes 28 and 29 are formed of copper regions of level M1.
A conductive bridge 30 (FIGS. 2A and 2C), formed of a copper track of level M2, creates a connection between lower end 10i of winding 10 (level M1) and upper electrode 28 of capacitor 12 (level M1). Conductive vias 31 and 32, crossing the insulating layer which separates level M2 from level M1, are provided to connect bridge 30 (level M2) to regions 10i and 28 (level M1).
At the surface of chip 20, contact areas 14 and 15 are provided to create connections to the outside. Passive integrated circuits are generally intended to be assembled to other electronic devices by means of bonding pads welded to areas 14 and 15. Thus, areas 14 and 15 are made of a conductive material specifically capable of receiving bonding pads, and especially having a good adherence to the pads. Such a material is currently designated in the art as a UBM, for “Under Bump Metallization”. It, for example, is a stack of a gold layer, of a copper layer, of a nickel layer, and of a titanium layer. Areas 14 and 15 are formed in openings made in an upper insulating layer which coats chip 20, and are in contact with copper regions 34 and 35 of metallization level M2. Region 34 is connected to bridge 30 by a conductive track of level M2, and region 35 is connected to outer end 10e of winding 10 (level M1) by a via 36.
Thus, inductance 10 is connected between areas 14 and 15, and series capacitors 12 and 13 are connected between areas 14 and 15, parallel to inductance 10.
In the chip manufacturing, all contact areas in the UBM material are made at the same time.
A disadvantage of this type of structure is that the chip manufacturing is relatively long and expensive. In particular, the forming of the metallizations of levels M1 and M2 comprises relatively long steps of electrolytic deposition of copper, resulting in a high cost of the chips.